Solid state memories (SSMs) provide an efficient mechanism for storing and transferring data in a wide variety of applications, such as hand-held portable electronic devices. Individual memory cells within such memories can be volatile or non-volatile, and can store data by the application of suitable write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read access operation by applying suitable read currents and sensing voltage drops across the cells.
The selection of specific memory cells in an SSM array can require complex circuitry with large numbers of interconnects and decoding logic elements to resolve individual data addresses. The complexity of such circuitry generally increases significantly as array size is increased.
As system designers seek to design SSM arrays with ever increased data storage capacities, including multi-layer 3D integrated arrays, the manufacturing costs of the associated selection circuitry, as well as the amount of overhead area required to accommodate the circuitry, generally increases as well.